Founding Note: The Thousand-Fold Gap

Published March 2026

The Problem

A single NVIDIA H100 GPU draws 700 watts at peak load. A rack of eight consumes 5,600 watts. A data center filled with thousands of them demands its own power substation. In 2024, global data centers consumed approximately 415 terawatt-hours of electricity — about 1.5% of all electricity generated on Earth — and the International Energy Agency projects this will more than double to 945 TWh by 2030, driven overwhelmingly by AI workloads.

Meanwhile, the human brain — processing visual scenes, coordinating motor functions, maintaining memories, and running language comprehension simultaneously — operates on roughly 20 watts. That is not a metaphor. It is a measurement. The brain achieves this through approximately 86 billion neurons communicating via sparse, asynchronous electrical pulses called spikes, with only a small fraction of neurons active at any given moment.

The efficiency ratio is staggering. Research from the Blue Brain Project estimates that biological neural computation is approximately 900 million times more energy-efficient than current artificial computing architectures. Even accounting for differences in task complexity, the gap is at minimum three orders of magnitude.

Why This Matters Now

Three converging pressures make this gap unsustainable:

1. The Power Wall. AI model sizes are doubling every few months, but chip power efficiency improves at roughly 1.4× per generation. We are building larger models faster than we can make them cheaper to run. The U.S. share of electricity devoted to data centers may triple from 4.4% to 12% by 2028.

2. The Edge Imperative. Autonomous vehicles, industrial robots, wearable medical devices, and IoT sensors all need real-time AI inference — but they cannot carry a 700-watt GPU and a cooling system. Edge AI demands milliwatt-scale processing that responds in microseconds, not milliseconds. SynSense's Speck chip has demonstrated face recognition at under 1 milliwatt with 3.36 microsecond spike latency — proving the paradigm works.

3. The Architecture Mismatch. Conventional chips process information through dense, synchronous clock cycles — every transistor switches every cycle, whether it has useful work or not. Biological neurons fire only when they have something to communicate. This event-driven sparsity is not a minor optimization; it is a fundamentally different computational paradigm.

What Cmospike Will Study

Our research focuses on spiking neural network (SNN) chip architectures built on mature CMOS process nodes. We chose this intersection deliberately:

• Spike encoding: How should analog signals from the real world — light, sound, pressure, temperature — be efficiently converted into temporal spike patterns that preserve information while minimizing energy? Current rate-coding approaches waste most of the theoretical efficiency advantage.
• On-chip learning: Backpropagation requires global error signals propagated through every layer — expensive in time, memory, and power. Biological synapses learn through local rules like spike-timing-dependent plasticity (STDP). Can hardware implementations of local learning rules match backpropagation accuracy for edge inference tasks?
• Hybrid integration: Pure neuromorphic chips excel at specific tasks but struggle with general control flow. How should SNN accelerators interface with conventional CMOS logic (RISC-V cores, standard peripherals) in a practical system-on-chip? Zhejiang University's Darwin3 chip — supporting 2.35 million neurons alongside a RISC-V management core — provides an instructive case study.
• Process node economics: Cutting-edge chip fabrication (3nm, 5nm) costs billions in tooling and yields diminishing returns for neuromorphic workloads where transistor density matters less than interconnect flexibility. Mature nodes like 28nm and 65nm offer 10-50× lower per-wafer cost. We study which architectural innovations unlock neuromorphic efficiency on accessible process technologies.

Our Approach

Cmospike is a research entity. We do not fabricate chips. We analyze, model, and publish.

Our work products are architecture analyses, benchmark comparisons, and design-space explorations that map the frontier between biological efficiency and silicon manufacturability. We believe the most valuable contribution at this stage is not another chip, but a clearer map of the design space — so that when the next generation of neuromorphic architects sits down at their workstations, they know which trade-offs matter and which don't.

We are not promising to build the future of computing. We are studying why the present architecture is running into a wall, and where the cracks are widest.