Active Research
Spike Encoding Benchmark
Status: In Progress
How should real-world signals — images, audio, sensor data — be translated into spike trains for neural computation? The choice of encoding scheme fundamentally determines the efficiency ceiling of any SNN system. This project benchmarks rate coding, temporal coding, and population coding approaches across standardized inference tasks on 28nm and 65nm CMOS targets.
Metrics:
- Energy per inference (pJ/operation)
- Encoding latency (clock cycles to first spike)
- Information retention vs. spike sparsity trade-off
- For which task categories does STDP achieve competitive accuracy?
- What is the silicon area overhead of on-chip STDP vs. storing pre-trained weights?
- Can hybrid approaches (backpropagation for training, STDP for fine-tuning) offer the best trade-off?
- SNN accelerator as peripheral (memory-mapped, DMA-driven)
- Tightly coupled SNN-CPU with shared cache
- Disaggregated chiplet approach (SNN die + logic die)
Benchmark framework under development.
STDP vs. Backpropagation for Edge Learning
Status: Scoping
Spike-timing-dependent plasticity (STDP) is biology's learning rule. Backpropagation is deep learning's. Can STDP — implemented directly in CMOS circuits — replace backpropagation for on-chip learning at the edge? This project compares the two approaches on inference accuracy, silicon area, and power consumption for targeted edge workloads.
Research questions:
Hybrid Integration Methodology
Status: Early Research
Neuromorphic accelerators don't replace conventional processors — they augment them. This project develops design methodologies for integrating SNN accelerator blocks into conventional CMOS SoC architectures, addressing the bus interface, memory hierarchy, and workload partitioning challenges.
Target architectures:
Power Wall Literature Survey
Status: Complete
A comprehensive review of the energy efficiency limits of conventional von Neumann architectures for neural network inference, establishing the theoretical and practical motivation for spike-based alternatives. This survey covers 150+ papers spanning CMOS scaling trends, memory wall analysis, and neuromorphic architecture proposals.
Available as internal reference document.